Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to read-only memory (ROM), which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of ROM that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a memory array which includes a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Each of the cells within an EEPROM memory array can be electrically programmed in a random basis by charging the floating gate. The charge can also be randomly removed from the floating gate by an erase operation. Charge is transported to or removed from the individual floating gates by specialized programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that is typically erased and reprogrammed in blocks instead of one byte at a time. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The data in a cell is determined by the presence or absence of the charge in the floating gate. The cells are usually grouped into sections called “erase blocks.” Each of the cells within an erase block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation.
The memory cells of both an EEPROM memory array and a Flash memory array are typically arranged into either a “NOR” architecture (each cell directly coupled to a bit line) or a “NAND” architecture (cells coupled into “strings” of cells, such that each cell is coupled indirectly to a bit line and requires activating the other cells of the string for access).
A problem in floating gate memory cell arrays is the issue of overerased memory cells. A floating gate memory cell is structurally similar to a MOSFET transistor, with a control gate separated from a channel, source, and drain by an insulator. In addition, embedded in the insulator is an isolated floating gate. As in a MOSFET transistor, current flows when the floating gate memory cell/transistor is selected or activated, charge trapped on the floating gate affects the amount of current flow in the floating gate transistor, effectively raising or lowering its threshold. In programming or erasing a floating gate memory cell, charge is transported to or from the electrically insulated floating gate of the floating gate transistor. If too much charge is removed from the floating gate of the floating gate transistor/memory cell it will flow current even when it is not selected. Floating gate transistors in this overerased state can affect current flow on shared bitlines and/or memory strings and thus potentially corrupt data read from other memory cells these common bitlines and/or memory strings.
In addition, as integrated circuit processing techniques improve, manufacturers try to reduce the feature sizes of the devices produced and thus increase the density of the IC circuits and memory arrays. In floating gate memory arrays in particular, the channel length of the floating gate memory cells that make up the memory array and spacing between memory cells in the strings have a large effect on the number of memory cells that can be placed in a given area and thus a direct impact on the density of the array and size of the resulting memory device.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a method and architecture for producing a more closely spaced and, thus, higher density floating gate memory array with improved overerasure handling properties.